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A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With \ll - 16 dB Return Loss Over 10 GHz Bandwidth

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9 Author(s)
Kossel, M. ; IBM Zurich Res. Lab., Ruschlikon ; Menolfi, C. ; Weiss, J. ; Buchmann, P.
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A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation is independent of the impedance tuning. To achieve a return loss of <-16 dB up to 10 GHz a 40 mum times 40 mum T-coil complements the transmitter output. This half-bit-rate clock SST transmitter has a duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations. The chip consumes 96 mW at 8.5 Gb/s and occupies 180 mum times 360 mum. In addition to the transmitter design, guidelines for the T-coil design are presented.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 12 )