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Wafer level packaging technology development for CMOS image sensors using Through Silicon Vias

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9 Author(s)
J. Charbonnier ; CEA-LETI, MINATEC, 17 rue des Martyrs, 38054 Grenoble Cedex 9 - France ; D. Henry ; F. Jacquet ; B. Aventurier
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In this paper a low temperature dasiavia-lastrdquo technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the steps of the through silicon vias (TSV) technology will be presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. In a second part, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. Morphological and electrical characterizations of the via-last technology will then be showed and discussed. Finally, a picture obtained with the TSV CMOS image sensor (TSV CIS) will be presented.

Published in:

Electronics System-Integration Technology Conference, 2008. ESTC 2008. 2nd

Date of Conference:

1-4 Sept. 2008