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Performance analysis and improvement for hybrid CMOS-SET circuit architectures

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2 Author(s)
Guoqing Deng ; Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON ; Chunhong Chen

Hybrid CMOS-SET circuit architectures, which combine the merits of SET and CMOS devices, promise to be a more practical implementation for nanometer-scale circuit design. In this work we discuss and compare two popular hybrid CMOS-SET architectures - serial and parallel - in terms of power dissipation, drivability and temperature effects. We use MIB compact model for SET devices and BSIM3v3 Spectre model for MOSFET transistors in order to simulate hybrid CMOS-SET circuits in Cadence environment with CMOS 180 nm technology. We also propose a hybrid NOR gate with parallel CMOS-SET architecture.

Published in:

Microsystems and Nanoelectronics Research Conference, 2008. MNRC 2008. 1st

Date of Conference:

15-15 Oct. 2008