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A 2.4-GHz +25dBm P-1dB linear power amplifier with dynamic bias control in a 65-nm CMOS process

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12 Author(s)
Po-Chih Wang ; Realtek Semicond. Corp., Hsinchu ; Kai-Yi Huang ; Yu-Fu Kuo ; Ming-Chong Huang
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A 2.4 GHz linear CMOS power amplifier (PA) for OFDM WLAN application in 65 nm CMOS technology is presented. The cascode PA operating from 3.3 V employs the proposed asymmetric lightly doped drain MOSFET (A-LDD) structure as common-gate stage to sustain large signal stress and 1.2 V core device as common source stage to provide high frequency operation. Beside, dynamic bias technique is used not only to increase efficiency but also improve the linearity. In the measurement, the breakdown voltage of the A-LDD MOSFET can achieve 6.2 V compared to standard I/O device of 5 V. A PA EVM of -29 dB is achieved at output power of 17 dBm with DC current of 173 mA from 3.3 V supply. Also, it reveals the output P1 dB of PA is 25.3 dBm.

Published in:

Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

Date of Conference:

15-19 Sept. 2008