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A low-power programmable dynamic frequency divider

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3 Author(s)
Chabloz, J. ; Swiss Center for Electron. & Microtechnol. (CSEM), Neuchatel ; Ruffieux, D. ; Enz, C.

In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic is proposed. By cascading compact dual-modulus divider slice with recursive feedback mechanisms, any dividing ratio is easily implemented. A 5-stages 0.18 mum CMOS implementation demonstrates a power consumption factor as low as 235 nW/MHz under 1.2 V supply for high dividing ratios.

Published in:

Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

Date of Conference:

15-19 Sept. 2008