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A 64 kbit SRAM with dual port dual width was fabricated in a 1P9M 90 nm CMOS technology. The narrow port has a width of 32 bits, the wide port has 256 bits. To minimise the leakage current a lowered secondary supply is applied to all inactive cells. The fine granular implementation allows the leakage currents to be reduced while the wake-up delay overhead is kept minimal. This system also includes a monitoring and regulation solution to minimise leakage currents while guaranteeing data retention on a die to die basis. Measurements show the SRAM is able to operate with a 2ns access time and is capable of a factor 2 leakage current reduction at a nominal 1V supply using a local series regulator.