A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis

Increasing V_th variation leads to the deterioration of SRAM operating stability, and accurate stability analysis is required in todaypsilas SRAM design. For the first time, we defined SRAM dynamic operating margins, which is more accurate than conventional static operating margin. The dynamic operating margin analysis is applied to a low-voltage SRAM module design. The SRAM module uses a memory-cell-activation time control with short bit-line structure for both read and write stability improvement. The SRAM module also uses body-bias control by column for further low-voltage operation, which is suitable for DVFS operation. A prototype SRAM module with body-bias control achieved 0.6-V operation.