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In this paper, we present a new read assist technique for SRAM to improve bitcell read stability. The new technique utilizes selective precharge where different parts of the bitlines are precharged to VDD or GND. Using charge sharing, the required value of bitline voltage can be precisely set to increase bitcellspsila SNM, while using only one supply voltage. A 512 kb memory was designed to demonstrate this technique in an industrial 45 nm technology. Results show large improvement in SNM and high robustness against process variations. In addition, the proposed technique reduces the memory access time compared to the conventional approach. Moreover, the proposed technique demonstrates higher operating margin which makes it an attractive option to deal with SRAM read stability in nanometer technologies.