Referenced Items are not available for this document.
The range of SRAM multi-bit upsets (MBU) in sub-100 nm technologies is characterized using irradiation tests on two prototype ICs, developed in 90 nm commercial processes. Results reveal that MBU, as large as 13-bit, can occur in these technologies, limiting the efficacy of conventional SEC-DED error-correcting codes (ECC). A double-error correcting (DEC) ECC implementation technique suitable for SRAM applications is presented. Results show that this DEC scheme reduces errors by 98.5% compared to only 44% reduction by conventional SEC-DED ECC.
Published in:
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European
Date of Conference: 15-19 Sept. 2008
- Page(s):
- 222 - 225
- ISSN :
- 1930-8833
- E-ISBN :
- 978-1-4244-2362-0
- Print ISBN:
- 978-1-4244-2361-3
- INSPEC Accession Number:
- 10394727
- Conference Location :
- Edinburgh
- Digital Object Identifier :
- 10.1109/ESSCIRC.2008.4681832
- Product Type:
- Conference Publications
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