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A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS

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5 Author(s)
Anders, M. ; Circuit Res. Lab., Intel Corporationm Hillsboro, Hillsboro, OR ; Kaul, H. ; Hansson, M. ; Krishnamurthy, R.
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An on-die multi-core circuit-switched network for tera-scale computing, achieving 2.9 Tb/s throughput for random data transmissions on a 64 core 2D mesh and consuming 8 W in 45 nm CMOS at 1.0V, 50degC is described. Use of pipelined circuit-switched transmission, coupled with circuit path queue circuits and packet-switched request circuits enable power consumption of 125 mW/router and efficiency of 363 Gb/s/W, with scalable traffic-dependent throughput up to 6.2 Tb/s.

Published in:

Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

Date of Conference:

15-19 Sept. 2008