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Strained Si/SiGe devices offer a route to high speed digital devices. Analog design trade-offs can also be improved using strained Si if device self-heating can be controlled; strained Si is generated using a strain relaxed buffer (SRB) of SiGe which has a lower thermal conductivity compared with bulk Si. In this work the impact of the SiGe SRB thickness on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self heating at high power levels leads to negative self gain and anomalous circuit behavior in terms of nonlinear phase shifts. By using ac and dc measurements we show that by reducing the SRB thickness self-heating effects are significantly lower and the analog design space is improved. The range of gate voltages that leverage positive self gain in 100 nm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by 100% compared with strained Si devices fabricated on conventional SRBs 4 mum thick. Guidelines for the maximum SRB thicknesses required to obtain positive self gain for highly scaled technology generations where self-heating effects increase are presented. For a 22 nm technology node, the SRB thickness should not exceed 20 nm for 1.5 V drain voltage and gate overdrive. The thin SRB is grown using a C-layer and does not compromise any aspect of device performance.
Date of Conference: 15-19 Sept. 2008