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Implementation of low power one-chip MUSE (HDTV) video processor using consumer oriented macros, etc

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7 Author(s)
T. Aoki ; Fujitsu Labs. Ltd., Japan ; N. Kadomaru ; O. Kamo ; T. Iwayoshi
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We describe the development of a one-chip video MUSE decoder by reducing the circuit size from 230000 gates to 160000 gates through logic optimization, memory reconfiguration, and the development of specialized macros. The low power design allowed us to mount the chip on inexpensive plastic packages

Published in:

IEEE Transactions on Consumer Electronics  (Volume:41 ,  Issue: 3 )