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Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation

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4 Author(s)
Hoppe, B. ; Siemens AG, Muenchen, West Germany ; Neuendorf, G. ; Schmitt-Landsiedel, D. ; Specks, W.

Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 3 )

Date of Publication:

Mar 1990

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