Cart (Loading....) | Create Account
Close category search window

Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hoppe, B. ; Siemens AG, Muenchen, West Germany ; Neuendorf, G. ; Schmitt-Landsiedel, D. ; Specks, W.

Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 3 )

Date of Publication:

Mar 1990

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.