Fully integrated current-mode CMOS gated baseline restorer circuits

Design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR for each of the three gated integrator channels is a differential current-in to single ended current-out circuit with a correction bandwidth of 100 kHz set by a 40 pF on-chip capacitor using pole splitting techniques. The BLRs for the constant fraction discriminator (CFD) constant fraction and arming comparators are differential current-in to voltage-out. Circuits with correction bandwidths of 5 MHz and 1 MHz set by on-chip capacitors of 10 pF and 2.5 pF respectively. The BLR circuits are capable of correcting differential input current offsets of /spl plusmn/40 /spl mu/A for the gated integrator circuits, /spl plusmn/100 /spl mu/A for the CFD constant fraction comparator circuit, and /spl plusmn/160 /spl mu/A for the CFD arming comparator circuit. Use of the BLR circuits allows photomultiplier tube (PMT) detector inputs to be ac coupled and all slow (gated integrator) and fast (CFD timing) signal processing channels to be dc coupled. The BLR circuits correct for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offset currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integration period. CFD constant fraction comparator input offset is maintained at submillivolt levels, and arming comparator threshold is maintained at a 0-0.48 V level under on-board DAC control.<
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