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A Parallel Architecture for Sampling Rate Conversion Based on Pseudo-DFT

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3 Author(s)
Qiang Yuan ; Southwest Electron. & Telecommun. Technol. Res. Inst., Chengdu ; Yuanling Huang ; Jiangtao Yu

A parallel processing architecture for sampling rate conversion in all-digital receiver is proposed in this paper. According to the time shifting property of the FT, the DFT of the desired output samples can be evaluated by the input samples. And the DFT-like transform in this constructed expression can be fast computed by the famous butterfly structure. To overcome the inherent saddle error of this approach, an overlapping input signal strategy is given.

Published in:

2008 4th International Conference on Wireless Communications, Networking and Mobile Computing

Date of Conference:

12-14 Oct. 2008