This paper describes a low-power piecewise linear A/D converter. A 5 MHz @ 5 V with 25 mW power consumption prototype has been implemented in a 1.5 μm CMOS process. The die area excluding pads is 5 mm2 . 11-bit absolute accuracy is obtained with a new DC offset plus charge-injection compensation technique used in the comparators scheme. This ADC with large dynamic range and high resolution is developed for the readout of a tracker and/or preshower in the future LHC experiments
Published in:
Nuclear Science, IEEE Transactions on
(Volume:42
,
Issue:
4
)
Date of Publication: Aug 1995