Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Design and performance of an analogue VLSI cell for pixel detector readout: ANAPIX

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

An analogue VLSI cell for hybrid pixel detector readout, ANAPIX, has been designed and tested. The chip has been manufactured in the FASELEC SACMOS 3 micron technology. A peak detector allows asynchronous signals to be processed without precise trigger timing. An equivalent noise charge of about 100 electrons r.m.s. has been achieved on the cell alone. The cell has been wire bonded to a silicon detector pixel matrix and in the laboratory energy spectra from radioactive gamma and beta sources have been recorded with an equivalent noise charge of 200 electrons rms. The dynamic range design target of 500 to 50000 electrons was not achieved yet, due to a non linearity around 4000 electrons. This problem is to be solved in the design of the second generation to be manufactured in a one micron technology. This new cell is to be connected via bump bonding to a detector, the first assemblies are expected to be ready in 1995

Published in:

Nuclear Science, IEEE Transactions on  (Volume:42 ,  Issue: 4 )