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Logic simulation with current-limited switches

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3 Author(s)
G. Ruan ; Analogy Inc., Beaverton, OR, USA ; J. Vlach ; J. A. Barby

A switch-level logic simulator for MOS networks based on the theory of current-limited switches is described. It was derived from a switch-level timing simulator by suppressing time-related information and by eliminating invalid events. The simulator obeys Kirchoff's laws and after initialization every node has a known voltage. It can thus be used to drive analog simulation. Fault simulation is easily incorporated by representing the line-open fault by an open circuit and the node-short fault by a short circuit. Examples demonstrate application to both logic and fault simulation

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:9 ,  Issue: 2 )