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Thermal modeling of on-chip interconnects and 3D packaging using EM tools

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9 Author(s)
Lijun Jiang ; IBM T. J. Watson Research Center, 1101 Kichawan Road, P.O. Box 208, Yorktown Heights, NY 10598, USA ; Seshadri Kolluri ; Barry J. Rubin ; Howard Smith
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The green (low power) chip design demands dramatic thermal and electrical simulation capabilities. In this paper, a novel thermal simulation approach for automatic thermal modeling of very large problems is introduced. This methodology can be fully integrated with existing solvers for electrical simulations, and make it possible to analyze practical on-chip and packaging thermal problems using the existing electromagnetic tools and geometry definitions, with very small additional effort. Its various applications to BEOL (on-chip wiring), thermal guideline design, and 3D integration (for multiple chip stacks) thermal modeling are investigated in this paper. We will demonstrate this capability with an automatic modeling framework, ChipJoule, for representative cases.

Published in:

2008 IEEE-EPEP Electrical Performance of Electronic Packaging

Date of Conference:

27-29 Oct. 2008