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Compact on-chip wire models for the clock distribution of high-speed I/O interfaces

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5 Author(s)

A lumped wire model is proposed for on-chip clock in the low-power and multi-gigahertz IO clock distributions. Ignoring the skin effect and inductive forward coupling, this model can be easily extracted using QuickCap and FastHenry, instead of more computing intensive full-wave solvers. Surrounding power/ground and signal wires within a 1000-mum window are all included in this model. The resulting SPICE netlist and simulation accurately model multiple current returns and the proximity effect at high frequencies. This model is validated with measured S-parameter up to 20 GHz using a 90 nm testing chip. The effective loop inductance is shown to have 2times frequency variations which impacts directly on the peak frequency of an LC resonance clock distribution.

Published in:

Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP

Date of Conference:

27-29 Oct. 2008

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