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This paper proposes a hierarchical and adaptive finite-element reduction-recovery method for power and signal integrity analysis of high-speed IC and packaging structures. This method rigorously reduces the matrix of a multilayer system of O(N) to that of a single-cell one of O(1) regardless of the original problem size. More important, the matrix reduction is achieved analytically, and hence the CPU and memory overheads are minimal. In addition, the reduction preserves the sparsity of the original matrix. As a result, the matrix factorization cost of the proposed method is reduced to a constant. The CPU cost at each time step scales linearly with the number of unknowns to be recovered. Furthermore, an adaptive reduction-recovery scheme is developed to perform reduction and recovery in the active layers only, and hence further reducing the complexity of the proposed method. Numerical and experimental results demonstrate its performance.