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Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance

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4 Author(s)
Sakian, P. ; Electr. Eng. Dept., Sharif Univ. of Technol., Tehran ; Saffari, M. ; Atarodi, M. ; Tajalli, A.

A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 m CMOS technology and operating in 10 Gbps data rate, the entire circuit consumes 52 mW.

Published in:

Circuits, Devices & Systems, IET  (Volume:2 ,  Issue: 5 )