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A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation

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3 Author(s)
Jian-Ming Huang ; Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung ; Chia-Chuan Lee ; Chua-Chin Wang

This paper presents a novel architecture for direct digital frequency synthesizer (DDFS) based on a modified parabolic polynomial interpolation method. A 16-segment parabolic polynomial interpolation is adopted to replace conventional ROM-based phase-to-amplitude conversion methods. Besides, the proposed parabolic polynomial interpolation is realized in a multiplier-less fashion such that the speed can be significantly improved. The proposed DDFS is implemented in a standard 0.13 mum cell-based technology. The maximum clock rate is 227 MHz, and the core area is 0.25 mm2. The simulation result shows that the spurious free dynamic range (SFDR) is 117 dBc.

Published in:

Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on

Date of Conference:

Aug. 31 2008-Sept. 3 2008