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A wide-range, low-power delay-locked loop based (DLL-based) frequency multiplier with the PMOS active load and adaptive body biasing (ABB) circuit is proposed. Adding the PMOS active load in the delay cells has the inductive-peaking effect to increase the operation frequency range. With the clocked-power ABB current mode logic (CML) exclusive-OR (XOR) circuit, the frequency multiplier can achieve power saving to 54.9% compared with convention CML XOR circuits. This is achieved by reducing the supply voltage to 1 V and dc-level of the differential inputs, while maintaining the original swing of differential outputs. The frequency multiplier can generate N times of frequency of the input clock when the number of delay cells (N) in the voltage control delay line (VCDL) is even. The proposed DLL-based frequency multiplier can operate from 80 MHz to 2.64 GHz using 0.18 mum CMOS process. The measured peak-to-peak jitters of the DLL core are 30.56 ps at 330 MHz and 70 ps at 80 MHz. The power consumption and jitter of the proposed frequency multiplier at 2.64 GHz are 27.79 mW and 23.5 ps, respectively.
Date of Conference: Aug. 31 2008-Sept. 3 2008