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An efficient static random access memory (SRAM) is presented in this paper. By using a newly developed architecture based on ldquopreequalizerdquo scheme, the geometry ratio between the pull-up and pull-down driver transistors of conventional 6-T cell will be similar to that of familiar inverter, thereby making the SRAM be provided with an improved read static noise margin (SNM) and a reduced cell area. The removal of DC path resulting from preequalize also yields significant power reduction. To avoid a write speed degradation caused by the internal race on cell current between the pull-up driver transistor and access transistor, a write-power-off scheme is proposed. To further decrease the write power consumption, data drivers are connected to the bit lines instead of the conventional power supply terminals. A 4-kb-capacity test prototype has been designed in a 0.18-mum CMOS process. Achievable power reduction for the proposed SRAM is approximately 16% according to the post-layout simulation results (with the parasitics extracted), compared to that designed in the conventional architecture.