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A design-oriented mathematical model for integrated DC/DC buck converters is presented in this paper. The analysis takes into account the main conduction power loss due to the switches channel resistance in on-state and, starting from the efficiency specification and other constraints, sets the guidelines for the sizing of the output power stage of the DC/DC converter. The model also considers the design of the driver stages, calculates the switching power loss and adjusts the efficiency to obtain the effective value. A CMOS DC/DC converter with Pulse Frequency Modulation (PFM) control in Discontinuous Conduction Mode (DCM) has been designed following such a criteria, validating the accuracy of the model in different loading conditions.