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While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the Alpha-Power Law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100MSPS CMOS current steering Digital-to-Analog Converter (DAC) with the Alpha-Power Law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control-switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8 V, 0.18 mum, 1-poly, 5-metal CMOS technology. It occupies 0.52 mm2 of silicon area with 15.8 mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.