By Topic

Constant multiplier design using specialized bit pattern adders

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Kyung-Ju Cho ; Div. of Electron.&Inf. Eng., Chonbuk Nat. Univ., Jeonju ; Suhyun Jo ; Yong-Eun Kim ; Yi-Nan Xu
more authors

The problem of efficient hardware implementation of multiple constant multiplication (MCM) is encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements in area and power consumption. In this paper, we present efficient implementation method of two common subexpressions (101, 101) in canonic signed digit (CSD) representation. By Synopsys simulations of a radix-24 FFT example, it is shown that the area, speed and power consumption can be reduced up to 21%, 11% and 12%, respectively, by the proposed algorithm.

Published in:

Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on

Date of Conference:

Aug. 31 2008-Sept. 3 2008