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Low error truncated multipliers for DSP applications

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5 Author(s)
Garofalo, V. ; Dept. of Electron. & Telecommun. Eng., Univ. of Napoli "Federico II" Napoli, Naples ; Petra, N. ; De Caro, D. ; Strollo, A.G.M.
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The paper presents a new technique to design signed and unsigned truncated multipliers. Simple formulae are developed in the paper to describe the truncated multiplier with minimum mean square error for every inputspsila bit-width. With respect to previously proposed techniques, our analytical approach is more general and improves the accuracy of the multiplier. We have also compared the accuracy achievable with the proposed truncated multiplier with respect to the accuracy of a standard full-width multiplier in a typical DSP application. The results show that the proposed multiplier causes only a negligible loss in accuracy. On the other hand, the area and the power dissipation of the DSP datapath are both improved by 16%.

Published in:

Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on

Date of Conference:

Aug. 31 2008-Sept. 3 2008

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