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A Low-Power mmWave CML Prescaler in 65nm SOI CMOS Technology

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5 Author(s)

A 5-stage CML prescaler operating up to 84 GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.40 power-delay product per gate. The prescaler's phase noise gain degeneration at the sensitivity curve boundary is reported for the first time.

Published in:

Compound Semiconductor Integrated Circuits Symposium, 2008. CSIC '08. IEEE

Date of Conference:

12-15 Oct. 2008