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A highly linear wideband power amplifier IC with low memory effect for W-CDMA applications is presented utilizing Si LDMOS process technology. The IC was optimized to reduce typical low frequency gain peak often observed in LDMOS power devices. Topology of the interstage matching contributes to reduction of the electrical memory effect to specification level of maximum 2 dB imbalance over power between upper and lower Adjacent Channel Power Ratio when using II-tone wideband modulated signal. The on-chip temperature compensation circuitry tracks the active device temperature characteristic without degradation of the linearity or worsens the memory effect. The measured gain of the IC was 28.5 dB and 3-dB bandwidth of 600 MHz around 2100 MHz was achieved. The IC attained -50 dBc ACPR at 5 W output power. At power level of 45 W and IMD3 = -30 dBc (two-tone) the IC exhibited power densities in excess of 469 mW/mm, in which matching losses were included. The IC demonstrated state-of-the-art RF power performance in terms of good linearity, low memory effects, well-suppressed low frequency gain peak and temperature tracking without linearity and IMD balance degradation.