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Integrated Circuit designers are typically constrained by layout "rules" which can sometimes appear arbitrary. The layout rules are generally accepted as logical requirements for manufacturability. Deciding appropriate rules normally involves a combination of experiments and experiences. Process engineers typically have a very good understanding of the capability of their tools, and they will add margin to increase the manufacturability. This work provides data behind some specific layout rules in order to establish relationships between the design and important quality parameters such as yield & defect density.