By Topic

Ultra low power analog standard cell for low frequency CMOS filters design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Kulej, T. ; Dept. of Electr. Eng., Tech. Univ. of Czestochowa, Czestochowa

A novel approach to very low frequency filters design in CMOS technology has been described in the paper. This approach is based on the application of a new universal analog cell, which can be configured as second order filter, gyrator etc. The circuit is designed in 0.35 mum n-well technology and consumes only 3 nW of power for nominal biasing current. The supply voltage is equal to 1 V with additional auxiliary biasing voltage equal to -1 V. The performance is verified by SPICE simulations.

Published in:

Signals and Electronic Systems, 2008. ICSES '08. International Conference on

Date of Conference:

14-17 Sept. 2008