Ultra low power analog standard cell for low frequency CMOS filters design

A novel approach to very low frequency filters design in CMOS technology has been described in the paper. This approach is based on the application of a new universal analog cell, which can be configured as second order filter, gyrator etc. The circuit is designed in 0.35 mum n-well technology and consumes only 3 nW of power for nominal biasing current. The supply voltage is equal to 1 V with additional auxiliary biasing voltage equal to -1 V. The performance is verified by SPICE simulations.