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A 1 Mb embedded 2T-SONOS Flash macro is implemented in 0.13 um logic compatible process. The Flash macro has improved reliability and yield with a power-on Successive Approximated Read Calibration (SARC). Word-line decoder area is greatly reduced using 1.8 V transistors to tolerate high voltage. Source degenerated compensation is implemented to enhance read margin. The Flash macro consumes 1.0 mA at 50 ns 1.8 V access and 0.5 uA in standby mode, and achieves one million cycling and 20-year data retention.