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45nm high-k + metal gate strain-enhanced CMOS transistors

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1 Author(s)
Chris Auth ; Logic Technology Development, Intel Corp., Hillsboro, OR, U.S.A.

At the 45 nm technology node, high-k + metal gate transistors were introduced for the first time on a high-volume manufacturing process [1]. The introduction of a high-k gate dielectric enabled transistors with a 0.7x reduction in Tox (electrical gate oxide thickness) while reducing gate leakage 1000x for the PMOS and 25x for the NMOS transistors. Dual-band edge workfunction metal gates were introduced, eliminating polysilicon gate depletion and providing compatibility with the high-k gate dielectric. High-k + Metal gates have also been shown to have improved variability at the 45 nm node [2]. In addition to the high-k + metal gate, the 35 nm gate length CMOS transistors have been integrated with a third generation of strained silicon and have demonstrated the highest drive currents to date for both NMOS and PMOS. An SRAM cell size of 0.346 mum2 has been achieved while using 193 nm dry lithography. High yield and reliability has been demonstrated on multiple single, dual-, quad- and six-core microprocessors.

Published in:

2008 IEEE Custom Integrated Circuits Conference

Date of Conference:

21-24 Sept. 2008