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A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

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6 Author(s)
Ting-Chen Wei ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu ; Wei-Chang Liu ; Chi-Yao Tseng ; Syu-Siang Long
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An OFDM baseband receiver chip for DVB-T/H application is proposed in this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200 ppm sampling clock offset (SCO) and plusmn 50 subcarrier spacing carrier frequency offset (CFO) in multipath environment. The total memory requirement of this chip is 102.8 KB and the total equivalent gate count (including memory) is about 806,800 gates. By using 0.18 mum CMOS process, the power consumption is 28 mW at 1.45 V, 40 MHz and core size of this chip is 3600 mum times 3600 mum.

Published in:

Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE

Date of Conference:

21-24 Sept. 2008