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Modeling of triple-well isolation and the loading effects on circuits up to 50 GHz

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2 Author(s)
Piljae Park ; High-Speed Silicon Lab, University of California, Santa Barbara, 93106-9560, USA ; C. Patrick Yue

This paper presents the noise isolation characteristics and substrate loading effects of NMOS devices in triple-well (TW) at frequencies up to 50 GHz. The importance of the series resistance in well bias path is investigated. Our study reveals that using large well bias resistors, which create a high substrate impedance, are beneficial to circuit performance in both saturation and triode bias regimes. However, small bias resistances are advantageous for better substrate noise isolation. By using test circuits designed in a 0.13-mum CMOS technology, a compact model for TW substrate impedance is developed to facilitate quantitative analyses. The dependence of TW isolation effectiveness on the bias resistance, well capacitance, and noise frequency are evaluated. To measure the impact of TW on circuit performances, the output impedance of a saturation-mode device and the insertion loss (IL) between source and drain of a triode-mode device are examined under different biasing conditions.

Published in:

2008 IEEE Custom Integrated Circuits Conference

Date of Conference:

21-24 Sept. 2008