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Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz

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2 Author(s)
Parastoo Nikaeen ; Stanford University, CA, USA ; Boris Murmann

A digital technique for the compensation of dynamic nonlinearities at the front-end of high-speed, high-resolution ADCs is presented. The complexity of the digital post-processing scheme is minimized using judicious modeling of the relevant nonidealities. Applying the method to a 14-bit, 155-MS/s ADC provides > 83 dB SFDR up to fin = 470 MHz. The post-processing block is estimated to consume 52 mW and occupy 0.54 mm2 in 90-nm CMOS.

Published in:

2008 IEEE Custom Integrated Circuits Conference

Date of Conference:

21-24 Sept. 2008