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A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS

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2 Author(s)
Proesel, J.E. ; Carnegie Mellon Univ., Pittsburgh, PA ; Pileggi, L.T.

A 0.6-to-1 V inverter-based 5-bit flash ADC in 90 nm digital CMOS is presented. Single-ended comparators are formed using digital inverters and resistors. The comparators are designed for compatibility with nanoscale CMOS lithography. A single-ended flash architecture was used without a front-end sample-and-hold. The ADC achieves a low frequency effective number of bits (ENOB) between 4.08 bits and 4.45 bits without calibration. Voltage scaling is demonstrated by 60 MS/s, 300 MS/s, and 600 MS/s operation at 0.6 V, 0.8 V, and 1 V, respectively. Power scales from 1.3 mW to 6.7 mW.

Published in:

Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE

Date of Conference:

21-24 Sept. 2008