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A test-chip in a low-power 45 nm technology, featuring uniaxial strained Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured and analyzed. Delay is characterized using an array of ring-oscillators and transistor leakage current is measured with an on-chip ADC. Results show that systematic variations are small and layout-induced variation is dominated by strain effects.