Referenced Items are not available for this document.
A test-chip in a low-power 45 nm technology, featuring uniaxial strained Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured and analyzed. Delay is characterized using an array of ring-oscillators and transistor leakage current is measured with an on-chip ADC. Results show that systematic variations are small and layout-induced variation is dominated by strain effects.
Published in:
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Date of Conference: 21-24 Sept. 2008
- Page(s):
- 129 - 132
- E-ISBN :
- 978-1-4244-2019-3
- Print ISBN:
- 978-1-4244-2018-6
- INSPEC Accession Number:
- 10392489
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/CICC.2008.4672038
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
