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Error correction for multi-level NAND flash memory using Reed-Solomon codes

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3 Author(s)
Bainan Chen ; Case Western Reserve University, 10900 Euclid Ave., Cleveland, OH 44106-7071, USA ; Xinmiao Zhang ; Zhongfeng Wang

Prior research efforts have been focusing on using BCH codes for error correction in multi-level cell (MLC) NAND flash memory. However, BCH codes often require highly parallel implementations to meet the throughput requirement. As a result, large area is needed. In this paper, we propose to use Reed-Solomon (RS) codes for error correction in MLC flash memory. A (828, 820) RS code has almost the same rate and length in terms of bits as a BCH (8248, 8192) code. Moreover, it has at least the same error-correcting performance in flash memory applications. Nevertheless, with 70% of the area, the RS decoder can achieve a throughput that is 121% higher than the BCH decoder. A novel bit mapping scheme using gray code is also proposed in this paper. Compared to direct bit mapping, our proposed scheme can achieve 0.02 dB and 0.2 dB additional gains by using RS and BCH codes, respectively, without any overhead.

Published in:

2008 IEEE Workshop on Signal Processing Systems

Date of Conference:

8-10 Oct. 2008