By Topic

A Highly Scalable Capacitorless Double Gate Quantum Well Single Transistor DRAM: 1T-QW DRAM

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. GÜnhan Ertosun ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA ; Pawan Kapur ; Krishna C. Saraswat

We propose a new kind of capacitorless DRAM: 1Transistor Quantum Well structure, which has a ldquostorage pocketrdquo for holes within the body. This memory gives the opportunity to engineer spatial hole distribution within the body of the device, which is not possible with the conventional 1T-DRAMs. Using this novel device, we demonstrate approximately two order-of-magnitude increase in the drain-current (Id) difference between the reads of two states of the memory.

Published in:

IEEE Electron Device Letters  (Volume:29 ,  Issue: 12 )