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A Highly Scalable Capacitorless Double Gate Quantum Well Single Transistor DRAM: 1T-QW DRAM

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3 Author(s)
Ertosun, M.G. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA ; Kapur, Pawan ; Saraswat, K.C.

We propose a new kind of capacitorless DRAM: 1Transistor Quantum Well structure, which has a ldquostorage pocketrdquo for holes within the body. This memory gives the opportunity to engineer spatial hole distribution within the body of the device, which is not possible with the conventional 1T-DRAMs. Using this novel device, we demonstrate approximately two order-of-magnitude increase in the drain-current (Id) difference between the reads of two states of the memory.

Published in:

Electron Device Letters, IEEE  (Volume:29 ,  Issue: 12 )