By Topic

A Novel Orthogonal Gate EDMOS Transistor With Improved dv/dt Capability and Figure of Merit (FOM)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

13 Author(s)
Hao Wang ; Dept. of Mater. Sci. & Eng., Toronto Univ., Toronto, ON ; H. P. Edward Xu ; Wai Tung Ng ; Kenji Fukumoto
more authors

A transistor with an orthogonal gate (OG) electrode is proposed to improve dv/dt capability, reduce the gate-to-drain overlap capacitance (C gd), and improve figure of merit (FOM). The OG has both a horizontal section and a vertical section for MOS gate control. This 30-V device is implemented in a 0.18-mum CMOS-compatible process. Comparing to a conventional extended drain MOSFET transistor with the same voltage rating and device size, four times higher dv/dt capability and 53% improvement in FOM are observed.

Published in:

IEEE Electron Device Letters  (Volume:29 ,  Issue: 12 )