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Buffering Interconnect for Multicore Processor Designs

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3 Author(s)
Yifang Liu ; Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX ; Jiang Hu ; Weiping Shi

Recently, the microprocessor industry is headed in the direction of multicore designs in order to continue the chip performance growth. We investigate buffer insertion, which is a critical timing optimization technique, in the context of an industrial multicore processor design methodology. Different from the conventional formulation, buffer insertion in this case requires a single solution to accommodate different scenarios, since each core has its own parameters. If conventional buffer insertion is performed for each scenario separately, there may be a different solution corresponding to each of these scenarios. A straightforward approach is to judiciously select a solution from one scenario and apply it to all the scenarios. However, a good solution for one scenario may be a poor one for another. We propose several algorithmic techniques for solving these multiscenario buffer insertion problems. Compared with a straightforward extension of the conventional buffer insertion, our algorithm can improve slack by 20-280 ps for max-slack solutions. For min-cost solutions, our algorithm causes no timing violation, while the extended conventional buffering results in 35% timing violations. Moreover, the computation speed of our algorithm is faster.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:27 ,  Issue: 12 )