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A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs

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2 Author(s)
Hosung Kim ; Tabula, Inc., Santa Clara, CA ; Lillis, J.

It is well known that optimizations made by traditional logic synthesis tools often correlate poorly with post-layout performance; this is largely a result of interconnect effects only being visible after layout. In this paper, a corrective methodology is proposed for timing-driven logic restructuring at the placement level. The approach focuses on a lookup table (LUT)-based field programmable gate arrays. The approach is iterative in nature. In each iteration, using current placement information, the method induces a timing-critical fan-in tree via (temporary) replication. Such trees are then reimplemented where the degrees of freedom include functional decomposition of LUTs, ldquomini-LUTrdquo tree mapping, and physical embedding. A dynamic programming algorithm optimizes over all of these freedoms simultaneously. All simple disjoint LUT decompositions (i.e., Ashenhurst style) are encoded in a ldquomini-LUTrdquo tree using choice nodes similar to those in the paper by Lehman At the same time, because embedding is done simultaneously, interconnect delay is directly taken into account. Over multiple iterations, the design is progressively improved. The framework has been implemented, and promising experimental results are reported.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:27 ,  Issue: 12 )

Date of Publication:

Dec. 2008

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