We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Block-level thermal model for floorplan stage in VLSI design flow

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shun-Hua Lin ; Dept. of Commun. Eng., Nat. Chiao Tung Univ., Hsinchu ; Jin-Tai Yan ; Herming Chiueh

Thermal issues have become a determinant factor to result in very large scale integrated (VLSI) circuits work or malfunction. For this reason, the paper proposed an efficient block-level thermal model for temperature calculation in the floorplan stage among the integrated circuit (IC) design flow. Furthermore, the model accurately profiles the temperature difference between all thermal blocks and overcomes the very long computational time issue existing in traditional tile-based thermal model. We not only prove the timing complexity by theory but also use five floorplan benchmarks to test our model. Observing the experimental results, the temperature calculation times for all benchmarks are really direct ratio of total amount of blocks. Hence our block-level thermal model really can reduce the temperature calculating time and provide useful temperature differences for rearranging the floorplan.

Published in:

Thermal Inveatigation of ICs and Systems, 2008. THERMINIC 2008. 14th International Workshop on

Date of Conference:

24-26 Sept. 2008