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The accurate and reproducible measurement of the junction-to-case thermal resistance Rth-JC of power semiconductor devices is far from trivial. In the recent time several new approaches to measure the Rth-JC have been suggested, among them transient measurements with two different interface layers between the package and a heat-sink. The Rth-JC can be identified either in the structure functions or at the point of separation of the two Zth-curves or their derivatives. Further investigations revealed however that the latter approach is restricted to power packages with solder die attach and cannot be applied to devices with thermally low conductive glue die attach since an internal heat flow barrier falsifies the measurement result. After recapitulating the transient dual interface measurement and its evaluation using the derivatives of the Zth curves, a detailed investigation of this method by means of finite element simulations is presented herein.