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Current paper proposes a new hierarchical approach to defect-oriented testing of CMOS circuits. The method is based on critical area extraction for identifying the possible shorted pairs of nets on the basis of the chip layout information, combined with logic-level test pattern generation. The novel contributions of the paper are a new bridging fault simulator and a test pattern generator, which are able to handle defects creating feedbacks into the circuit. As a preprocessing step, a combined stuck-at test set from two different test pattern generators implementing alternative strategies (pseudorandom and deterministic) were created. Nevertheless, many short defects were not covered by this extended stuck-at approach. Analyses carried out in this paper show that the stuck-at tests are not covering up to 4% of the shorts (both testable and untestable). The test coverage (fault efficiency) can be increased by the new generator by up to 0.4% in comparison to full stuck-at test. Layout analysis for a set of benchmarks has been performed. The experiments indicate how the number of bridging faults of non-zero probability is dependent on the circuit size.