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It has been shown that several process parameters encounter variation in the very deep submicron era. Due to the increased power and performance variability, a multi-objective variability-aware yield optimization method is crucial. However, most of current yield optimization methods use greedy single objective optimization approach. In this paper, a comprehensive and multi-objective yield optimization framework is proposed to consider the effects of both power and performance yield degradation. In other words, an evolutionary gate sizing optimization approach is introduced to be used in the proposed framework to enhance yield, significantly. Compared with recent yield optimization algorithms and, the proposed framework leads to better results for the attempted circuits. In addition, the independency of proposed framework on selected power and delay analysis techniques makes it suitable for future investigations as using dual threshold voltage assignment approach.