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Asynchronous design has become more and more popularin last years. Many tools and design methodologies have been developed for this kind of circuits. Unfortunately only few of them are focused on their implementation onto FPGAs. Nowadays FPGAs are widespread in many applications and they have enough complexity to allow prototyping also complex designs. For this reason this paper is focused on the implementation of asynchronous-specific blocks on programmable devices using conventional tools and flows. It offers solutions for implementing Muller C elements and delay chains onto FPGAs avoiding unwanted behavior given by the synthesis and the fitting phases. This paper also introduces the solution adopted in our co-design environment to automatically generate delay chains used to single-rail implementation of asynchronous circuits. This is a part of our project which aims at developing a complete framework for producing asynchronous circuits from Simulink models.
Date of Conference: 3-5 Sept. 2008